Tushar Krishna is an Assistant Professor in the School of ECE at Georgia Tech since 2015. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007).
Before joining Georgia Tech, Dr. Krishna spent a year as a post-doctoral researcher at Intel, Massachusetts, and a semester at the Singapore-MIT Alliance for Research and Technology.
Dr. Krishna’s research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus area is in architecting the interconnection networks and communication protocols for efficient data movement within computer systems, both on-chip and in the cloud.
Contact: tushar <at> ece <dot> gatech <dot> edu
Hyoukjun Kwon received the B.S. degree in Computer Science and Engineering (CSE) and Environmental Materials Science (EMS) from Seoul National University (SNU) in 2015.
He joined Georgia Tech as a CS Ph.D. student in 2015.
His research interests are in interconnection networks for emerging computer systems and hardware including heterogeneous systems, accelerators, and multichip packages.
Contact: hyoukjun <at> gatech <dot> edu
Mayank Parasar received the B.Tech (Hons) in Instrumentation Engineering from Indian Institute of Technology (IIT), Kharagpur in 2013.
Following his bachelors, Mayank worked at NVidia India, Bangalore Design Center performing architectural validation of NVidia’s in-house CPU for 2 years.
He joined Georgia Tech as an ECE PhD candidate in 2015. He is also the recipient of “Otto & Jenny Krauss Fellow” award at Georgia Tech.
Mayank received the M.S. degree from the School of Electrical and Computer Engineering at Georgia Tech in 2017.
His research interests include Network on Chip (NoC), memory systems and system software/application layer co-design.
Contact: mparasar <at> gatech <dot> edu
Ananda Samajdar received a B.Tech. (Hons) in Electronics and Communication engineering from Indian Institute of Information Technology (IIIT), Allahabad in 2013.
He also worked in the CHiPES lab at NTU, Singapore in the final semester of his undergrad.
Following his bachelors, Ananda worked at Qualcomm India, Bangalore Design Center in the SoC integration and power teams as a front-end VLSI engineer for 3 years.
He joined Georgia Tech as an ECE PhD student in 2016.
His research focusses on computer architecture, with an emphasis on interconnect networks and accelerator design for machine learning workloads. He is also highly interested in deep learning algorithms and VLSI design.
Contact: anandsamajdar <at> gatech <dot> edu
Eric Qin received his B.S. degree in Electrical Engineering from Arizona State University (ASU) in 2017.
He joined Georgia Tech as an ECE PhD candidate in 2017.
Eric’s research interests include interconnection networks, deep learning accelerators, machine learning, and computer architecture.
Contact: ecqin <at> gatech <dot> edu
Sheng-Chun (Felix) Kao
Sheng-Chun (Felix) Kao received his B.S and M.S. degrees in Electrical Engineering from National Taiwan University in 2017.
He joined Georgia Tech as an ECE Ph.D. student in 2018.
Felix’s research interests include deep learning accelerators, machine learning, computer architecture, interconnection networks, and VLSI design.
Contact: felix <at> gatech <dot> edu
- Yehowshua Immanuel (BS-MS, ECE, Expected: Spring 2019)
- Fei Wu (BS-MS, ECE, Expected: Spring 2019)
- Winner of Georgia Tech President’s Undergraduate Research Award (PURA) for Summer 2017
- Roberto Guirado (BSc, UPC Spain) – Spring 2019
- Sachit Kuhar (BTech, IIT Guwahati) – Summer 2018
- Zhongyuan Zhao (PhD, SJTU) – Fall 2017 to Spring 2018
Zhongyuan Zhao received the B.S. degree in Electronic Information Engineer from Harbin Institute of Technology in 2012. He is a PhD student in ECE at the Shanghai JiaoTong University.
He was a visiting student in Georgia Tech hosted by professor Tushar Krishna from Aug 2017 to Aug 2018.
Zhongyuan’s research focuses on compiler and architecture design for merging computing system such as reconfigurable computing system and DNN accelerators.
Contact: zyzhao.sjtu <at> gmail <dot> com
- Parth Mannan (MS, ECE, 2018)
- Thesis: Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware
- First Employment: NVIDIA
- Srikant Bharadwaj (MS, ECE, 2017)
- Thesis: Scaling Address Translation in Multi-core Architectures using Low-Latency Interconnects
- First Employment: AMD Research (GPU Micro-architecture)
- Brian Lebiednik (MS, CS, 2017)
- First Employment: Instructor, Army Cyber Institute, West Point
- Aniruddh Ramrakhyani (MS, ECE, 2017)
- Thesis: Deadlock Recovery in On-Chip Interconnection Networks
- First Employment: Apple
- Parth Mannan (MS, ECE, 2018)
- Sergi Abadal (UPC, Spain)
- Arkaprava Basu (Indian Institute of Science)
- Abhishek Bhattacharjee (CS, Yale University)
- Paul Gratz (ECE, Texas A&M)
- Swati Gupta (ISyE, Georgia Tech)
- Natalie Enright Jerger (ECE, University of Toronto)
- Nachiket Kapre (ECE, University of Waterloo)
- Sung-Kyu Lim (ECE, Georgia Tech)
- Mikko Lipasti (ECE, Univ of Wisconsin, Madison)
- Joshua San Miguel (ECE, Univ of Wisconsin, Madison)
- Saibal Mukhopadhyay (ECE, Georgia Tech)
- Umakishore Ramachandran (CoC, Georgia Tech)
- Vivek Sarkar (CoC, Georgia Tech)
- Madhavan Swaminathan (ECE, Georgia Tech)
- Kamakoti Veezhinathan, G S Madhusudan, Neel Gala, Rahul Bodduna (IIT Madras Shakti Project)
- Brad Beckmann (AMD Research)
- Michael Pellauer (NVIDIA Research)
- Sudarshan Srinivasan, Dipankar Das, Bharat Kaul (Intel)
- Paul Whatmough (ARM Research)