We strongly believe in enabling researchers to perform rapid design-space exploration and prototyping of novel microarchitectures. To this end, we have developed and released the following open-source design tools.

Please email Tushar Krishna if you need any information about any of these tools.

Networks-on-Chip (NoC) for Many-core SoCs

Link Description Language Papers
garnet Network-on-Chip and Network-on-Package Model inside the gem5 full system simulator C++


DAC 2020

OpenSMART Parameterizeable NoC RTL generator  Bluespec
(generates Verilog)

Deep Learning Accelerator Modeling Frameworks

Link Description Language Papers
Union Optimizer in MLIR for Accelerator Mapping/HW DSE C++ PACT 2021
GAMMA DiGamma Specialized Genetic Algorithms for Mapping and HW resource optimization for DNN Accelerators C++

ICCAD 2020

DATE 2022

MAESTRO Analytical Model for Deep Learning Dataflows C++ MICRO 2019
SCALE-sim Systolic Array Simulator  C++ ISPASS 2020
STONNE Cycle-level simulator for flexible Dense and Sparse DNN Accelerators  C++ IISWC 2021
ASTRA-Sim Deep Learning Distributed Training Simulator C++ ISPASS 2020 ISPASS 2022

Deep Learning Accelerator RTL

Link Description  Language  Papers
SIGMA Sparse and Irregular GEMM Accelerator  Verilog HPCA 2020
MAERI DNN Accelerator with Reconfigurable Interconnects Bluespec
(generates Verilog)
Microswitch-NoC NoC specialized for DNN Accelerators Bluespec
(generates Verilog)
NOCS 2017

The whole is greater than the sum of its parts