Principal Investigator
Tushar Krishna is an Associate Professor in the School of ECE at Georgia Tech since 2015. He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007).
Before joining Georgia Tech, Dr. Krishna spent a year as a post-doctoral researcher at Intel, Massachusetts, and a semester at the Singapore-MIT Alliance for Research and Technology.
Dr. Krishna’s research spans the computing stack: from circuits/physical design to microarchitecture to system software. His key focus area is in architecting the interconnection networks and communication protocols for efficient data movement within computer systems, both on-chip and in the cloud.
Contact: tushar <at> ece <dot> gatech <dot> edu
Post-doctoral Researchers
PhD Students
Srikant Bharadwaj earned his B.E.(Hons.) from BITS Pilani, India in 2014 and M.S from Georgia Institute of Technology in 2017 before joining Synergy lab as a PhD student. Srikant is also a senior researcher at AMD Research, and his primary research field there is computer architecture.
Srikant’s research interests include on-chip interconnects and GPU microarchitecture. He has several publications and patents in the field of GPU microarchitecture, Network-on-Chips, and Quantum Computing. He maintains the Garnet3.0 Network-on-chip simulator within gem5. In addition to AMD, he has also worked in several architectural roles in organizations such as NVIDIA, Apple, and Sun Microsystems.
Contact: srikant.bharadwaj <at> amd <dot> com
Saeed Rashidi received his BS from Shiraz University in 2015, and his MS from Sharif University of Technology in 2017, both in Computer Engineering. He joined Georgia Tech in Spring 2019 to start his PhD in Electrical & Computer Engineering.
His research interests are DNN Training/Inference Accelerators, Scalable Training HW/SW co-design, ML algorithms and Domain-Specific accelerator design in general.
Contact: saeed <dot< rashidi <at> gatech <dot> edu
Geonhwa Jeong received a B.S. degree in Creative IT Engineering (CiTE) and Computer Science and Engineering (CSE) from Pohang University of Science and Technology (POSTECH) in 2019. He joined Georgia Tech as a Computer Science (CS) Ph.D. student in 2019.
His research interests include hardware-software co-design for emerging DNNs, accelerator design, heterogeneous architecture, and interconnection networks.
Contact: geonhwa <dot< jeong <at> gatech <dot> edu
William (Jonghoon) Won received his B.S. degree in Computer Science and Engineering (CSE) from Seoul National University (SNU) in 2019. He joined Georgia Tech as a Computer Science (CS) Ph.D. student in 2019.
His research interests include DNN accelerator designs, DNN software-hardware co-design, machine learning, big data analytics, and interconnection networks.
Contact: william.won <at> gatech <dot> edu
Raveesh Garg received his BE(Hons) degree in Electronics and Instrumentation Engineering from Birla Institute of Technology and Science (BITS), Pilani, Pilani Campus, India in 2019. He joined Georgia Tech as an ECE graduate student in Fall 2019 and joined the Synergy Lab in Fall 2020.
His research interests include Computer Architecture, On-chip Networks and Domain Specific Hardware Architectures for AI and Scientific applications.
Contact: raveesh.g <at> gatech <dot> edu
Jianming Tong received B.E. degree in Electrical Engineering (EE) from Xi`an Jiaotong University supervised by Prof. Pengju Ren in 2020. After spending 8 months as a research assistant in Tsinghua University supervised by Prof. Yu Wang, he joined the Georgia Tech as a Computer Science (CS) Ph.D. student in Spring 2021.
His research interest include domain-specific architecture, on-chip network and robotics..
Contact: jtong45 <at> gatech <dot> edu
Abhimanyu Bambhaniya
Abhimanyu Bambhaniya received his B.Tech. (with Honors) in Electronics and Communication Engineering from the Indian Institute of Technology, Roorkee (IITR) in 2019.
From 2019-21, Abhimanyu worked at Alphaics, Bangalore, a startup developing an AI engine for edge-inference applications for two years after his bachelor’s. There he worked on SoC tape-out on 16nm FFC. He was part of the team responsible for Neural Engine’s design, power, area optimization, and SoC implementation on FPGA and ASIC.
He joined Georgia Tech as an ECE Ph.D. student in Fall 2021.
Abhimanyu’s research focuses on Computer Architecture, specifically efficient accelerators for AI and related emerging applications,. He is also highly interested in deep learning algorithms and VLSI design. He likes to be informed on modern trends in semiconductors, quantum computing, and robotics. His hobbies include hiking, and visiting new places, and general reading (Psychology, History, and geography).
Contact: abambhaniya3 <at> gatech <dot> edu
Difei Cao
(Co-Advised with Kishore Ramachandran)
Jinsun Yoo
(Co-Advised with Kishore Ramachandran)
Canlin Zhang
MS Students
- Yangyu Chen (ECE)
Undergraduate Students
- David Pan (BS, ECE)
Visitors
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- Francisco Muñoz-Martínez (PhD, University of Murcia) – Fall 2021
- Jan Moritz Joseph (PhD, Otto-von-Guericke-Universität Magdeburg, Germany) – Fall 2019 to Spring 2020
- Roberto Guirado (BSc, UPC Spain) – Spring 2019
- Sachit Kuhar (BTech, IIT Guwahati) – Summer 2018
- Zhongyuan Zhao (PhD, Shanghai Jiaotong University) – Fall 2017 to Spring 2018
Alumni
PhD
- #5 Sheng-Chun (Felix) Kao (PhD, ECE, 2022)
- Thesis: Domain-aware Genetic Algorithms for Hardware and Mapping Co-Optimization for Efficient DNN Acceleration
- Key Open-source Artifacts from PhD:
- GAMMA – A Domain-aware Genetic Algorithm for Mapping DNNs on Accelerators (ICCAD 2020)
- DiGamma – A Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators (DATE 2022)
- ConfuciuX – Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning (MICRO 2020)
- MAGMA – An Optimization Framework for Mapping Multiple DNNs on Multiple Accelerator Cores (HPCA 2022)
- First Employment: Waymo
- Contact: felix <at> gatech <dot> edu
- #4 Eric Qin (PhD, ECE, 2022)
- Thesis: Building Efficient Tensor Accelerators for Sparse and
Irregular Workloads - Key Highlights from PhD:
- Best Paper Nominee at IPDPS 2022
- Best Paper at HPCA 2020
- Key Open-source Artifacts from PhD:
- SIGMA Verilog (HPCA 2020)
- HLS Generator for Sparse Accelerators
- First Employment: Meta
- Contact: ecqin <at> gatech <dot> edu
- Thesis: Building Efficient Tensor Accelerators for Sparse and
- #3 Ananda Samajdar (PhD, ECE, 2021)
- Thesis: Methodology and Analysis for Efficient Custom Architecture Design using Machine Learning
- Key Highlights from PhD:
- Best Paper at HPCA 2020
- Honorable Mention in IEEE Micro Top Picks 2019
- Silver Medalist at ACM Student Research Competition, ASPLOS 2019
- Finalist at ACM Student Research Competition, ASPLOS 2018
- Key Open-source Artifacts from PhD:
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- SCALE-sim DNN Accelerator Simulator (ISPASS 2020)
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- First Employment: IBM Research
- Contact: anandsamajdar <at> gatech <dot> edu
- #2 Mayank Parasar (PhD, ECE, 2020)
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- Thesis: Subactive Techniques for Guaranteeing Routing and Protocol Deadlock Freedom in Interconnection Networks
- Key Highlights from PhD:
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- Best Paper Nominee at SC 2021
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- Key Open-source Artifacts from PhD:
- First Employment: Samsung Austin Research Center
- Contact: mparasar <at> gatech <dot> edu
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- #1 Hyoukjun Kwon (PhD, SCS, 2020)
- Thesis: Data- and Communication-centric Approaches to Model and Design Flexible Deep Neural Network Accelerators
- Key Highlights from PhD:
- Honorable Mention at ACM SIGARCH / IEEE CS TCCA Outstanding Dissertation Award 2021
- Best Paper at HPCA 2020
- IEEE Micro Top Picks 2020
- Qualcomm Innovation Fellowship Finalist 2019
- Honorable Mention in IEEE Micro Top Picks 2019
- ACM Student Research Competition Finalist at MICRO 2018
- Key Open-source Artifacts from PhD:
- First Employment: Facebook Reality Labs
MS (Thesis)
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- Matthew Denton (MS, ECE, 2021)
- Thesis: Acceleration of Sparse Matrix Multiplication using Bit-Serial Arithmetic
- First Employment: Luminous Computing
- Yehowshua Immanuel (BS + MS, ECE, 2020)
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- Thesis: Plug-and-Play FOSS ML Accelerator: From Concept to Conception
- First Employment: Founder of ChipEleven (Startup)
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- Vineet Nadella (BS + MS, ECE, 2020)
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- Thesis: Investigating Opportunities and Challenges in Modeling and Designing Scale-Out DNN Accelerators
- First Employment: Amazon
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- Parth Mannan (MS, ECE, 2018)
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- Thesis: Exploring Opportunities and Challenges in Enabling Neuro-Evolutionary Algorithms in Hardware
- First Employment: NVIDIA
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- Srikant Bharadwaj (MS, ECE, 2017)
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- Thesis: Scaling Address Translation in Multi-core Architectures using Low-Latency Interconnects
- First Employment: AMD Research (GPU Micro-architecture)
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- Aniruddh Ramrakhyani (MS, ECE, 2017)
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- Thesis: Deadlock Recovery in On-Chip Interconnection Networks
- First Employment: Apple
- Now at Google
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- Brian Lebiednik (MS, CS, 2017)
- First Employment: Instructor, Army Cyber Institute, West Point
- Matthew Denton (MS, ECE, 2021)
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BS + MS