“The whole is greater than the sum of its parts” – Aristotle
The Synergy Lab focuses on architecting next-generation intelligent computer systems (whole) as an interconnection of compute and memory building blocks (parts). Our research spans all the way from the application layer to system software to microarchitecture to CAD to circuits, enabling cross-layer optimizations while maintaining abstractions.
- Computer Architecture
- Manycore Systems
- Heterogeneous SoCs
- Deep Learning Accelerators
- Interconnection Networks
- July 2017: Tushar teaching a week-long course on On-Chip Networks at the ACACES 2017 Summer School in Fiuggy, Italy
- June 2017: Book Release – On Chip Networks, Second Edition, Morgan Claypool Publishers, co-authored by Natalie Enright Jerger, Tushar Krishna and Li-Shiuan Peh, will be released at ISCA 2017.
June 2017: Paper on DVFS over SMART NoCs accepted in ICCAD 2017. Congrats Monodeep!
- May 2017: Tushar published an essay on The Future of Network-on-Chip (NoC) Architectures in the Circuit Cellar Magazine.
May 2017: Congrats to Aniruddh Ramrakhyani and Mayank Parasar for receiving their MS in ECE degrees at the GT Commencement.
May 2017: Tushar gave at talk at Baidu Research’s Silicon Valley AI Lab
April 2017: Tushar gave a talk at TAMU CESG Seminar Series
February 2017: SMART-LEES paper on CAD tool for III-V interconnects wins Best Paper Award at DATE 2017!
November 2016: SMART-LEES paper on CAD tool for III-V interconnects accepted in DATE 2017.
- October 2016: Tushar giving a talk at CMU CALCM Seminar Series.
- October 2016: Static Bubble NoC paper on deadlock-recovery accepted in HPCA 2017. Congrats Aniruddh!
- October 2016: Garnet2.0 released!
- Aug 2016: Welcome to ECE undergraduate Fei Wu.
- April 2016: Welcome Aniruddh Ramrakhyani as the lab’s first MS student.
- Jan 2016: Welcome Hyoukjun Kwon (CS) and Mayank Parasar (ECE) as the lab’s first two PhD students.
- Aug 2015: Prof. Tushar Krishna starts at Georgia Tech.