OpenSMART is a NoC RTL generator that provides a state-of-the-art low-latency NoCs based on SMART (Single-cycle Multi-hop Asynchronous Repeated Traversal) [1]. SMART enables multi-hop on-chip traversals within a single cycle, removing the dependence of latency on hops. SMART leverages wire delay of the underlying repeated wires, and augments each router with the ability to request and setup bypass paths.

OpenSMART takes SMART from a NoC optimization to a design methodology for SoCs, enabling users to generate verified RTL for a class of user-specified network configurations, such as network size, topology, routing algorithm, number of VCs/buffers, router pipeline stages, and so on.

OpenSMART also provides the ability to generate any heterogeneous topology with low and high-radix routers and optimized single-stage pipelines, leveraging fast logic delays in technology nodes today.

Papers

[1] Tushar Krishna, Chia-Hsin Owen Chen, Woo Cheol Kwon, and Li-Shiuan Peh, “Breaking the on-chip latency barrier using SMART,”  HPCA 2013. (paper)

[2] Hyoukjun Kwon and Tushar Krishna, “OpenSMART: Single-cycle Multi-hop NoC Generator in BSV and Chisel,” ISPASS 2017. (paper)

Slides

ISPASS 2017 (slides)

OpenSuCo 2017 (slides)

Code Repository

Repository Access Request: https://tinyurl.com/Get-OpenSMART