Tools

We strongly believe in enabling researchers to perform rapid design-space exploration and prototyping of novel microarchitectures. To this end, we have developed and released the following open-source design tools.

Networks-on-Chip (NoC) for Many-core SoCs

Link Description Language
garnet2.0 Network-on-Chip and Network-on-Package Model inside the gem5 full system simulator C++
OpenSMART Parameterizeable NoC RTL generator  Bluespec
(generates Verilog)

 

Deep Learning Accelerators

Link Description Language
MAESTRO Analytical Model for Deep Learning Dataflows C++
SCALE-sim Systolic Array simulator  C++
MAERI DNN Accelerator with Reconfigurable Interconnects Bluespec
(generates Verilog)
Microswitch-NoC NoC specialized for DNN Accelerators Bluespec
(generates Verilog)

 

The whole is greater than the sum of its parts