We strongly believe in enabling researchers to perform rapid design-space exploration and prototyping of novel microarchitectures and systems. To this end, we have developed and released the following open-source design tools.
Please email Tushar Krishna if you need any information about any of these tools.
AI/ML Distributed Platform Modeling Frameworks
| Link | Description | Language | Papers |
| Chakra | Distributed ML workload graph representation | Python | Arxiv |
| ASTRA-Sim | Distributed ML Communication Simulator | C++ | ISPASS 2023 ISPASS 2020 |
| GenZ | Platform Simulator for LLM Inference. Try Now | Python | Arxiv |
AI/ML Accelerator Modeling Frameworks
| Link | Description | Language | Papers |
| GAMMA DiGamma | Specialized Genetic Algorithms for Mapping and HW resource optimization for DNN Accelerators (works with MAESTRO and Timeloop) | Python | |
| MAESTRO | Analytical Model for Deep Learning Dataflows and Accelerators | C++ | MICRO 2019 |
| SCALE-sim | Cycle-level Simulator for Systolic Arrays | C++ | ISPASS 2020 |
| STONNE | Cycle-level simulator for flexible Dense and Sparse DNN Accelerators | C++ | IISWC 2021 |
AI/ML Accelerator RTL
| Link | Description | Language | Papers |
| FEATHER | Reconfigurable Accelerator with Data Layout Reordering Support | Verilog | ISCA 2024 |
| SIGMA | Sparse and Irregular GEMM Accelerator | Verilog | HPCA 2020 |
| MAERI | DNN Accelerator with Reconfigurable Interconnects | Bluespec (generates Verilog) | ASPLOS 2018 |
| Microswitch-NoC | NoC specialized for DNN Accelerators | Bluespec (generates Verilog) | NOCS 2017 |
Networks-on-Chip (NoC) for Many-core SoCs
| Link | Description | Language | Papers |
| garnet | Network-on-Chip and Network-on-Package Model inside the gem5 full system simulator | C++ | |
| OpenSMART | Parameterizeable NoC RTL generator | Bluespec (generates Verilog) | ISPASS 2017 |